Comparative analysis of adders hardware implementation on FPGA
Abstract
In this work we considered two types of adders for addition of two binary numbers implementation: carry propagate adders and parallel-prefix adders. In this article simulation on FPGA for both architectures and their comparative analysis is made. Simulation results for 4, 8, 16 and 32-bits circuits showed that parallel-prefix architecture using gives the gain in speed up to 41% compared to sequential architecture through increasing the hardware costs up to 71%. Parallel-prefix adders should use the for those applications, in which the maximization of speed is the main objective. On the other hand, carry propagate adder is better for hardware costs and power consumption decrease.
About the Authors
Nikolay Ivanovich Chervyakov
North Caucasus Federal University
Russian Federation
Russian Federation
Pavel Alekseyevich Lyakhov
North Caucasus Federal University
Russian Federation
Russian Federation
Maria Vasilevna Valueva
North Caucasus Federal University
Russian Federation
Russian Federation
O. V. Krivolapova
North Caucasus Federal University
Russian Federation
Russian Federation
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Review
For citations:
Chervyakov N.I., Lyakhov P.A., Valueva M.V., Krivolapova O.V. Comparative analysis of adders hardware implementation on FPGA. Science. Innovations. Technologies. 2016;(4):99-108. (In Russ.)
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