Preview

Science. Innovations. Technologies

Advanced search

Design of a Galois Field Multiplier Circuit using Quantum-dot Cellular Automata

Abstract

The Quantum-dot Cellular Automata (QCA) is a possible future of nano-electronics computing technology, that promises small size, low power, and fast digital circuits compared to the existing transistor-based designs. In this paper, design of a novel Galois Field (22) multiplier using QCA is presented. This is the first QCA implementation of multiplication GF (22), which can be used as one of the components of nano-electronics cryptography circuits, such as advanced encryption standard (AES). The proposed QCA circuit is verified and simulated using QCA Designer tool.

About the Authors

Maryam Jahantigh Akbarzadeh
University of Advanced Technology
Russian Federation


Amir Sabbagh Molahosseini
Islamic Azad University
Russian Federation


References

1. M. M. Eshaghian-Wilner, Bioinspired and Nanoscale Integrated Computing, Johan Wiley & Sons Publication, 2009.

2. C. S. Lent, P. D. Tougaw, W. Porod and G. H. Bernstein, «Quantum Cellular Automata», Nanotechnology, vol. 4, no. 1, pp. 49-57, 1993.

3. M. A.Garcia-Martinez, R. Posada-Gomez, G. Morales-Luna, and F. Rodriguez-Henriquez, «FPGA Implementation of an Efficient Multiplier over Finite Fields GF(2m)», In Proceedings of the International Conference on Reconfigurable Computing and FPGAs, 2005.

4. M. Mustafa, M. R. Beigh, «Design and implementation of quantum cellular automata based novel parity generator and checker circuits with minimum complexity and cell count», Indian Journal of Pure & Applied Physics, vol. 51, pp.60-66, 2013.

5. M. R. Beigh, M. Mustafa, F. Ahmad, «Performance Evaluation of Efficient XOR Structures in Quantum-Dot Cellular Automata (QCA)», Circuits and Systems, Scientific Research Publishing, vol. 4, pp. 147-156, 2013.

6. Tougaw, P., and C. Lent, «Logical Devices Implemented Using Quantum Cellular Automata», Journal of Applied Physics, vol. 75, pp. 1818- 1825, 1994.

7. E. N. Mui «Practical Implementation of Rijndael S-Box Using Combinational Logic», 2007, http://www.xess.com/projects/Rijndael_SBox.pdf.

8. X. Zhang, K. K. Parhi, «High-Speed VLSI Architectures for the AES Algorithm», IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 9, 2004.

9. M. Z. Moghadam and K. Navi, «Ultra-Area-Efficient Reversible Multiplier», Elsevier Microelectronics Journal, vol. 43, no. 6, pp. 377-385, 2012.


Review

For citations:


Akbarzadeh M.J., Molahosseini A.S. Design of a Galois Field Multiplier Circuit using Quantum-dot Cellular Automata. Science. Innovations. Technologies. 2015;(1):91-98. (In Russ.)

Views: 45


Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.


ISSN 2308-4758 (Print)